HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 733

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

No
No
No
Write transmit data in ICDRT
Write transmit data in ICDRT
No
No
No
Read ACKBR in ICIER
Read BBSY in ICCR2
Read TEND in ICSR
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
TRS to 0 in ICCR1
Write transmit data
Set MST and TRS
Write 1 to BBSY
Write 0 to BBSY
Figure 20.14
in ICCR1 to 1.
and 0 to SCP.
Set MST and
ACKBR=0 ?
BBSY=0 ?
TEND=1 ?
TDRE=1 ?
TEND=1 ?
STOP=1 ?
Last byte?
in ICDRT
Transmit
and SCP
Initialize
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Sample Flowchart for Master Transmit Mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Mater receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
[12] Clear the STOP flag.
[13] Issue the stop condition.
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
Test the status of the SCL and SDA lines.
Set master transmit mode.
Issue the start candition.
Set the first byte (slave address + R/W) of transmit data.
Wait for 1 byte to be transmitted.
Test the acknowledge transferred from the specified slave device.
Set the second and subsequent bytes (except for the final byte) of transmit data.
Wait for ICDRT empty.
Set the last byte of transmit data.
Rev. 3.00 Jan. 18, 2008 Page 671 of 1458
Section 20
I
2
C Bus Interface (IIC)
REJ09B0033-0300