HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 647

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI has single-channel serial communication interface with FIFO (SCIF) that supports
asynchronous serial communication. The SCIF can perform asynchronous and synchronous serial
communication. It also has 64-stage FIFO registers for both transmission and reception that enable
this LSI efficient high-speed continuous communication. Channel 0 operates as an IrDA interface
while optional module IrDA is used.
18.1
• Asynchronous or synchronous mode can be selected for serial communication mode.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
• Six types of interrupts (asynchronous mode):
• Two types of interrupts (synchronous mode)
• The direct memory access controller (DMAC) can be activated to execute a data transfer by a
• On-chip modem control functions (CTS and RTS)
• Transmit data stop function is available
• While the SCIF is not used, it can be stopped by stopping the clock for it to reduce power
• The number of data in the transmit and receive FIFO registers and the number of receive errors
• Channel 0 operates as an IrDA interface.
• Full-duplex communication capability
SCIS3C0C_000020030200
SCK pin (external)
Transmit-data-stop, transmit-FIFO-data-empty, receive-FIFO-data-full, receive-error (framing
error/parity error), break-receive, and receive-data-ready interrupts. A common interrupt vector
is assigned to each interrupt source.
transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
consumption.
of the receive data in the receive FIFO register can be known.
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
Section 18
Features
Serial Communication Interface with FIFO
Section 18
(SCIF)
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 585 of 1458
REJ09B0033-0300