HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 727

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(Master output)
20.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 20.9 and 20.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS bit in ICMR and the CKS4 to CKS0 bits in
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
(Master output)
(Slave output)
processing
ICCKS1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
with TDRE = 1. When TEND is set, clear TEND.
SCL
ICDRS
ICDRR
SDA
SDA
RDRF
RCVD
User
Slave Transmit Operation
Data n-1
Figure 20.8
A
[5] Read ICDRR after setting RCVD
9
Data n-1
Bit 7
1
Bit 6
2
Master Receive Mode Operation Timing (2)
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
[7] Read ICDRR,
6
and clear RCVD
Rev. 3.00 Jan. 18, 2008 Page 665 of 1458
Bit 1
7
Bit 0
Data n
Section 20
8
A/A
9
Data n
[6] Issue stop
condition
I
2
C Bus Interface (IIC)
REJ09B0033-0300
[8] Set slave
receive mode