HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 159

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(c)
• Repeat control instructions
• Load instructions for SR, RS, and RE registers
Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control
(d) Branching to an instruction following the repeat detection instruction and restriction
Execution of a repeat detection instruction must be completed without any branch so that the CPU
can recognize the repeat loop. Therefore, when the execution branches to an instruction following
the repeat detection instruction, the control will not be passed to a repeat start instruction after
executing a repeat end instruction because the repeat loop is not recognized by the CPU. In this
case, the RC[11:0] bits of the SR register will not be changed.
• If a conditional branch instruction is used in the repeat loop, an instruction before a repeat
• If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call
Here, a branch includes a return from an exception processing routine. If an exception whose
return address is placed in an instruction following the repeat detection instruction occurs, the
repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted
from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts
that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a
transition to an exception occurs but a program cannot be returned to the previous execution state
correctly. For details, refer to section 7, Exception Handling.
The following instructions must not be placed between the repeat start instruction and repeat
detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the
correct operation cannot be guaranteed.
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
detection instruction must be specified as a branch destination.
instruction must be placed before a repeat detection instruction.
Instructions prohibited during repeat loop (In a repeat loop consisting of four or more
instructions)
on an exception acceptance
instructions, and the external loop by other instructions such as DT or BF/S.
Rev. 3.00 Jan. 18, 2008 Page 97 of 1458
Section 3 DSP Operating Unit
REJ09B0033-0300