HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1482

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 3.00 Jan. 18, 2008 Page 1420 of 1458
REJ09B0033-0300
Item
25.5 EP4 Isochronous-Out
Transfer
Figure 25.14 EP4 Isochronous-
Out Transfer Operation (SOF is
Normal)
Figure 25.15 EP4 Isochronous-
Out Transfer Operation (SOF is
Broken)
25.6 EP5 Isochronous-In Transfer
Figure 25.16 EP5 Isochronous-In
Transfer Operation (SOF is
Normal)
Figure 25.17 EP5 Isochronous-In
Transfer Operation (SOF in
Broken)
25.9 Usage Notes
25.9.7 Note on Clock Frequency
Section 26 LCD Controller
26.1 Features
26.3 Register Description
26.3.1 LCDC Input Clock Register
(LDICKR)
26.3.10 LCDC Horizontal
Character Number Register
(LDHCNR)
863
880
Page Revision (See Manual for Details)
849,
890
852,
853
861
863
867
All “INTN” in the figures changed to “Interrupt request”.
All “INTN” in the figures changed to “Interrupt request”.
Section 25.9.7 added.
Representations of the bus clock and peripheral clock
are changed from Bck and Pck to Bφ and Pφ,
respectively.
Corrected
• Supports the selection of data formats (the endian
Added
This LCDC can select the bus clock (Bφ), the peripheral
clock (Pφ), or the external clock (LCD_CLK) as its
operation clock source.
Deleted
Notes:
1. The values set in HDCN and HTCN must satisfy the
setting for bytes, packed pixel method) by register
settings.
relationship of HTCN ≥ HDCN. Also, the total
number of characters of HTCN must be an even
number. (The set value will be an odd number, as it
is one less than the actual number.)