HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 198

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 DSP Operating Unit
Table 3.26 Correspondence between Operands and Registers
Note: The multiply operations basically generate 32-bit operation results. So when a register
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic operation. So,
the upper words of each multiplier and multiplicand are input into a MAC unit as shown in figure
3.16. In the SH’s standard multiply operations, the lower words of both source operands are input
into a MAC unit. The operation result is also different from the SH’s case. The SH’s multiply
operation result is aligned to the LSB of the destination, but the fixed-point multiply operation
result is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always
0.
The fixed-point multiply operation is executed in one cycle. Multiply is always unconditional, but
does not affect any condition code bits, DC, N, Z, V, and GT , in DSR.
• Overflow Protection
Rev. 3.00 Jan. 18, 2008 Page 136 of 1458
REJ09B0033-0300
Register
A0
A1
M0
M1
X0
X1
Y0
Y1
The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is
executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean
(+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF.
providing the guard-bit parts are specified as a destination operand, the guard-bit parts will
copy bit 31 of the operation result.
Se

Yes


Yes
Yes
Yes

Sf

Yes


Yes

Yes
Yes
Dg
Yes
Yes
Yes
Yes



