HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1475

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
20.3.5 I
(ICSR)
20.7 Usage Notes
Section 21 Serial I/O with FIFO
(SIOF)
21.1 Features
21.2 Input/Output Pins
Table 21.1 Pin Configuration
21.3 Register Descriptions
2
C Bus Status Register
Page Revision (See Manual for Details)
656
677
679
679
681
682
Changed
Changed
The falling edge of the ninth clock is recognized by
checking the SCLO bit in the I
(ICCR2).
Deleted
This LSI includes a clock-synchronized serial I/O
module with FIFO (SIOF) that comprises two channels.
The SIOF can perform serial communication with a
serial peripheral interface bus (SPI).
SPI mode deleted.
All descriptions related to SPI mode deleted.
SPI Control Register (SPICR) deleted.
Bit
3
Bit Name Description
STOP
Stop Condition Detection Flag
[Setting conditions]
•
•
[Clearing condition]
•
Rev. 3.00 Jan. 18, 2008 Page 1413 of 1458
In master mode: when a stop
condition is detected after frame
transfer is completed
In slave mode: when a stop
condition is detected after the
address set in SAR matches the
salve address that comes as the
first byte after the detection of a
start condition
When 0 is written in STOP after
reading STOP = 1
2
C bus control register 2
REJ09B0033-0300