HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 139

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.6.2
Table 2.12 shows the operation code map.
Table 2.12 Operation Code Map
Instruction Code
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0010
0010
Rn
Rn
Rn
Rn
Rn
Rn
Rm
Rm
Rn
0000
0000
0000
0000
0000
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
1. Number of states before the chip enters the sleep state.
2. For details, refer to section 7, Exception Handling.
Operation Code Map
Fx
Fx
00MD
01MD
10MD
11MD
00MD
10MD
Rm
00MD
01MD
Fx
Fx
Fx
Fx
Fx
Fx
Fx
Rm
Rm
Rm
Rm
Rm
LSB
0000
0001
0010
0010
0010
0010
0011
0011
01MD
1000
1000
1001
1010
1011
1000
1001
1010
1011
11MD
disp
00MD
01MD
10MD
Fx: 0000
MD: 00
STC
STC
STC
STC
BSRF
PREF
MOV.B
CLRT
CLRS
NOP
RTS
STS
MOV. B
MOV.L
MOV.B
MOV.B
TST
Rm
Rm, @(R0, Rn)
MACH, Rn
@(R0, Rm), Rn
Rm, @Rn
Rm, @–Rn
SR, Rn
SPC, Rn
R0_BANK, Rn
R4_BANK, Rn
@Rm
Rm, Rn
Rm, @(disp:4, Rn)
Fx: 0001
MD: 01
STC
STC
STC
MOV.W
SETT
SETS
DIV0U
SLEEP
STS
MOV.W
MOV.W
MOV.W
AND
GBR, Rn
Rm, @(R0, Rn)
MACL, Rn
@(R0, Rm), Rn
Rm, @Rn
Rm, @–Rn
R1_BANK, Rn
R5_BANK, Rn
Rm, Rn
Rev. 3.00 Jan. 18, 2008 Page 77 of 1458
MOV.L
STS
Fx: 0010
MD: 10
STC
STC
STC
BRA
CLRMAC
RTE
MOVT
MOV.L
MOV.L
MOV.L
XOR
Rm,@(R0, Rn)
PR, Rn
Rm, @–Rn
VBR, Rn
R2_BANK, Rn
R6_BANK, Rn
Rm
Rn
@(R0, Rm), Rn
Rm, @Rn
Rm, Rn
Fx: 0011 to 1111
MD: 11
STC
STC
STC
MUL.L
LDTLB
MAC.L
DIV0S
OR
REJ09B0033-0300
Section 2
SSR, Rn
Rm, Rn
R3_BANK, Rn
R7_BANK, Rn
@Rm+,@Rn+
Rm, Rn
Rm, Rn
CPU