HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 699

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.6
(1)
The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes
written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number
set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit
data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous
transmission.
However, if the number of data bytes written in SCFTDR is less than or equal to the transmit
trigger number, the TDFE flag will be set to 1 again after being cleared to 0. The TDFE flag
should therefore be cleared to 0 after a number of data bytes exceeding the transmit trigger number
has been written to SCFTDR.
The number of transmit data bytes in SCFTDR can be found in the bits 14 to 8 of the FIFO data
count set register (SCFDR).
(2)
The RDF flag in the serial status register (SCSSR) is set when the number of receive data bytes in
the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger
number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set,
receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient
continuous reception.
However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will
be set to 1 again after being cleared to 0. The RDF flag should therefore be cleared to 0 when 1
has been written to RDF after all receive data has been read.
The number of receive data bytes in SCFRDR can be found in the bits 6 to 0 of the FIFO data
count set register (SCFDR).
(3)
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set. Note that, although transfer of receive data to
SCFRDR is halted in the break state, the SCIF receiver continues to operate.
SCFTDR Writing and the TDFE Flag
SCFRDR Reading and the RDF Flag
Break Detection and Processing
Usage Notes
Section 18
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 637 of 1458
REJ09B0033-0300