HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 280

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Exception Handling
Figure 7.1 shows the bit configuration of each register.
7.1.1
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Rev. 3.00 Jan. 18, 2008 Page 218 of 1458
REJ09B0033-0300
Bit
31 to 10
9 to 2
1, 0
TRAPA Exception Register (TRA)
Bit Name

TRA

31
31
31
31
31
Initial
Value



Figure 7.1 Register Bit Configuration
R/W
R
R/W
R
0
0
0
0
TEA
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-bit Immediate Data
Reserved
These bits are always read as 0. The write value
should always be 0.
12 11
12 11
12 11
10 9
EXPEVT
INTEVT
INTEVT2
TRA
2 1 0
0
0
0
0
0
TRA
EXPEVT
INTEVT
INTEVT2
TEA