HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 428

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9
(6)
A write access ends in one cycle when data is written in non-cacheable region and the data bus
width is larger than or equal to access size.
Figure 9.18 shows the single write basic timing.
Rev. 3.00 Jan. 18, 2008 Page 366 of 1458
REJ09B0033-0300
Single Write
Bus State Controller (BSC)
Figure 9.18
A12/A11*
Notes:
D31 to D0
DACKn*
A25 to A0
RD/WR
DQMxx
CKIO
RAS
CAS
CSn
BS
1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
1
2
Basic Timing for Single Write (Auto-Precharge)
Tr
Tc1
Trwl
Tap

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