HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 790

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21
(2)
The transmit sources and receive sources are signals indicating the state; after being set, if the state
changes, they are automatically cleared by the SIOF.
When the DMA transfer is used, a DMA transfer request is pulled low (0 level) for one cycle at
the end of DMA transfer.
(3)
On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the
following operations.
• Transmit FIFO underflow (TFUDF)
• Transmit FIFO overflow (TFOVF)
• Receive FIFO overflow (RFOVF)
• Receive FIFO underflow (RFUDF)
• FS error (FSERR)
• Assign error (SAERR)
Rev. 3.00 Jan. 18, 2008 Page 728 of 1458
REJ09B0033-0300
The immediately preceding transmit data is again transmitted.
The contents of the transmit FIFO are protected, and the write operation causing the overflow
is ignored.
Data causing the overflow is discarded and lost.
An undefined value is output on the bus.
The internal counter is reset according to the FSYN signal in which an error occurs.
 If the same slot is assigned to both serial data and control data, the slot is assigned to serial
 If the same slot is assigned to two control data items, data cannot be transferred correctly.
Regarding Transmit and Receive Classification
Processing when Errors Occur
data.
Serial I/O with FIFO (SIOF)