HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 234

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Memory Management Unit (MMU)
(2)
This LSI supports a 29-bit physical address space. As shown in figure 4.5, the physical address
space is divided into eight areas. Area 1 is mapped to the on-chip module control register area and
on-chip memory area. Area 7 is reserved.
For details on physical address space, refer to section 9, Bus State Controller (BSC).
(3)
When the MMU is enabled, the virtual address space is divided into units called pages. Physical
addresses are translated in page units. Address translation tables in external memory hold
information such as the physical address that corresponds to the virtual address and memory
protection codes. When an access to area P1 or P2 occurs, there is no TLB access and the physical
address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB is searched
by virtual address and, if that virtual address is registered in the TLB, the access hits the TLB. The
corresponding physical address and the page control information are read from the TLB and the
physical address is determined.
If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing
will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in
external memory is searched and the corresponding physical address and the page control
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Physical Address Space
Address Transition
Figure 4.5 Physical Address Space
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
H'0000 0000
(On-chip registers and
On-chip memories)
(Reserved)
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7