HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1462

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 3.00 Jan. 18, 2008 Page 1400 of 1458
REJ09B0033-0300
Item
8.3.1 Interrupt Priority Registers A
to J (IPRA to IPRJ)
Table 8.2 Interrupt Sources and
IPRA to IPRJ
8.3.4 Interrupt Request Register 0
(IRR0)
8.3.5 Interrupt Request Register 1
(IRR1)
8.3.6 Interrupt Request Register 2
(IRR2)
Page Revision (See Manual for Details)
248
252
253
254
Amended
Note:
Changed
IRR0 is an 8-bit register that indicates interrupt
requests from the TMU and IRQ0 to IRQ5.
Deleted
IRR1 is an 8-bit register that indicates whether interrupt
requests from the DMAC and LCDC are generated.
Changed
IRR2 is an 8-bit register that indicates whether interrupt
requests from the SSL and LCDC are generated. This
register is initialized to H'00 by a power-on reset or
manual reset, but is not initialized in standby mode.
Note: On the models not having the SSL, the SSL-
related bits are reserved. The write value should always
be 0.
Added
Register
IPRD
IPRG
IPRJ
Bit
7
Bit
4
Bit Name

Bit Name Description
SSLIR
*
Reserved. Always read as 0. The write value
should always be 0. The SSL and SDHI -related
bits are effective only for the models that include
them. Reserved bits apply if they are not included.
Bits 15 to 12
Reserved*
SCIF0
Reserved*
Initial
Value
0
SSLI Interrupt Request
…
Note:
SSL, this bit is reserved and always read
as 0. The write value should always be 0.
R/W
R
On the models not having the
Bits 7 to 4
IRQ5
Reserved*
SDHI
Description
Reserved
This bit is always read as
0. The write value should
always be 0.
Bits 3 to 0
IRQ4
Reserved*
AFEIF