HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 725

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 20.7 and 20.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
(Master output)
(Master output)
(Slave output)
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
This enables the issuance of the stop condition after the next reception.
processing
SCL
SDA
SDA
ICDRT
ICDRS
TDRE
TEND
User
Master Receive Operation
[5] Write data to ICDRT
Figure 20.6
A
9
Bit 7
1
Bit 6
Master Transmit Mode Operation Timing (2)
2
Bit 5
3
Data n
Data n
Bit 4
4
Bit 3
5
Bit 2
6
Rev. 3.00 Jan. 18, 2008 Page 663 of 1458
[6] Issue stop condition. Clear TEND.
Bit 1
7
Section 20
Bit 0
8
[7] Set slave receive mode
A/A
9
I
2
C Bus Interface (IIC)
REJ09B0033-0300