HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 252

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Memory Management Unit (MMU)
• Software (TLB Protection Violation Handler) Operations
4.5.3
A TLB invalid exception results when the virtual address is compared to a selected TLB entry
address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception
processing includes both hardware and software operations.
• Hardware Operations
Rev. 3.00 Jan. 18, 2008 Page 190 of 1458
REJ09B0033-0300
J. Execution branches to the address obtained by adding the value of the VBR contents and
Software resolves the TLB protection violation and issues the RTE (return from exception
handler) instruction to terminate the handler and return to the instruction stream. Issue the RTE
instruction after issuing two instructions from the LDTLB instruction.
In a TLB invalid exception, this hardware executes a set of prescribed operations, as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
D. The PC value indicating the address of the instruction in which the exception occurred is
E. The contents of SR at the time of the exception are written into SSR.
F. The mode (MD) bit in SR is set to 1 to place the privileged mode.
G. The block (BL) bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way number causing the exception is written to RC in MMUCR.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100 to invoke the TLB protection violation exception handler.
EXPEVT register.
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the delayed branch instruction is written to the SPC.
H'0000 0100, and the TLB protection violation exception handler starts.
TLB Invalid Exception