HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 769

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame (slot number). SICDAR can be specified only when the FL bit in SIMDR is specified as
1xxx (x: Don't care.).
Bit
15
14 to 12
11
10
9
8
7
6 to 4
Bit Name
CD0E

CD0A3
CD0A2
CD0A1
CD0A0
CD1E

Initial
Value
0
All 0
0
0
0
0
0
All 0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
Description
Control Channel 0 Data Enable
0: Disables transmission and reception of control
1: Enables transmission and reception of control
Reserved
These bits are always read as 0. The write value should
always be 0.
Control Channel 0 Data Assigns 3 to 0
Specify the position of control channel 0 data in a
receive or transmit frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
•
Control Channel 1 Data Enable
0: Disables transmission and reception of control
1: Enables transmission and reception of control
Reserved
These bits are always read as 0. The write value should
always be 0.
channel 0 data
channel 0 data
channel 1 data
channel 1 data
Transmit data for the control channel 0 data is
specified in the SITD0 bit in SITCR.
Receive data for the control channel 0 data is stored
in the SIRD0 bit in SIRCR.
Rev. 3.00 Jan. 18, 2008 Page 707 of 1458
Section 21
Serial I/O with FIFO (SIOF)
REJ09B0033-0300