HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 679
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417320.pdf
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(4)
Figure 18.3 shows a sample serial transmission flowchart. After SCIF transmission is enabled, use
the following procedure to perform serial data transmission.
Transmitting and Receiving Data (Serial data transmission)
read 1 from TDFE bit and TEND flag
Write transmit data (16 - transmit
trigger set number) to SCFTDR,
Clear TE bit in SCSCR2 to 0
Read TEND bit in SCSSR2
Set SCPDR2 and SCPCR2
Read TDFE bit in SCSSR
in SCSSR, then clear to 0
All data transmitted?
End of transmission
Start transmission
Break output?
Figure 18.3
TEND= 1?
TDFE= 1?
Yes
Yes
Yes
Yes
(3)
Sample Serial Transmission Flowchart
No
No
No
No
(1)
(2)
Section 18
(1) SCIF status check and transmit data write:
(2) Serial transmission continuation procedure:
(3) Break output at the end of serial
Read serial status register (SCSSR) and
check that the TDFE flag is set to 1, then
write transmit data to the transmit FIFO
data register (SCFTDR), read 1 from the
TDFE and TEND flags, then clear these
flags to 0.
The number of transmit data bytes that can
be written is 64 - (transmit trigger set
number).
To continue serial transmission, read 1 from
the TDFE flag to confirm that writing is
possible, then write data to SCFTDR2, and
then clear the TDFE flag to 0.
transmission:
To output a break in serial transmission, set
the port SC data register (SCPDR) and port
SC control register (SCPCR), then clear the
TE bit to 0 in the serial control register
(SCSCR).
In steps 1 and 2, it is possible to ascertain
the number of data bytes that can be
written from the number of transmit data
bytes in SCFTDR indicated by the upper 8
bits of the FIFO data count set register 2
(SCFDR).
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 617 of 1458
REJ09B0033-0300
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