HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 56

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 9.13
Table 9.14
Table 9.15
Table 9.15
Table 9.16
Table 9.16
Table 9.17
Table 9.17
Table 9.18
Table 9.19
Table 9.20
Table 9.21
Section 10 Direct Memory Access Controller (DMAC)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Section 11 Clock Pulse Generator (CPG)
Table 11.1
Table 11.2
Table 11.3
Section 13 Power-Down Modes
Table 13.1
Table 13.2
Rev. 3.00 Jan. 18, 2008 Page lvi of lxii
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (2)-2..................................................................... 352
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (3) ........................................................................ 353
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (4)-1..................................................................... 354
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (4)-2..................................................................... 355
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (5)-1..................................................................... 356
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (5)-2..................................................................... 357
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (6)-1..................................................................... 358
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (6)-2..................................................................... 359
Relationship between Access Size and Number of Bursts.................................... 360
Access Address in SDRAM Mode Register Write ............................................... 380
Output Addresses when EMRS Command is Issued ............................................ 383
Relationship between Bus Width, Access Size, and Number of Bursts................ 386
Pin Configuration.................................................................................................. 409
Transfer Request Sources ..................................................................................... 423
Selecting External Request Modes with RS Bits .................................................. 426
Selecting External Request Detection with DL, DS Bits ...................................... 427
Selecting External Request Detection with DO Bit .............................................. 427
Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits ..... 429
Supported DMA Transfers.................................................................................... 434
Relationship between Request Modes and Bus Modes
by DMA Transfer Category.................................................................................. 441
Pin Configuration.................................................................................................. 457
Clock Operating Modes ........................................................................................ 458
Possible Combination of Clock Mode and FRQCR Values ................................. 459
States of Power-Down Modes .............................................................................. 478
Pin Configuration.................................................................................................. 479