HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 440

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9
(10) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-down mode by
bringing the CKE signal to the low level in the non-access cycle. This power-down mode can
effectively lower the power consumption in the non-access cycle. However, please note that if an
access occurs in power-down mode, a cycle of overhead occurs because a cycle that asserts the
CKE in order to cancel power-down mode is inserted.
Figure 9.27 shows the access timing in power-down mode.
Rev. 3.00 Jan. 18, 2008 Page 378 of 1458
REJ09B0033-0300
A12/A11*
Bus State Controller (BSC)
A25 to A0
D31 to D0
DACKn*
RD/WR
DQMxx
CKIO
CKE
CSn
RAS
CAS
BS
Notes:
1
2
Power-down
Figure 9.27
1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tnop
Access Timing in Power-Down Mode
Tr
Tc1
Td1
Tde
Tap
Power-down

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