HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 341

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. The BSC functions enable this LSI
to connect directly with SRAM, SDRAM, and other memory storage devices, and external
devices.
9.1
The BSC has the following features:
(1) External address space
• A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B,
• A maximum 64 Mbytes for each of the six areas, CS0, CS2 to CS4, CS5, and CS6, totally a
• Can specify the normal space interface, byte-selection SRAM, burst ROM (clock synchronous
• Can select the data bus width (8, 16, or 32 bits) for each address space.
• Controls the insertion of the wait state for each address space.
• Controls the insertion of the wait state for each read access and write access.
• Can set the independent idling cycle in the continuous access for five cases: read-write (in
(2) Normal space interface
• Supports the interface that can directly connect to the SRAM.
(3) Burst ROM (clock asynchronous) interface
• High-speed access to the ROM that has the page mode function.
CS6A and CS6B, totally 384 Mbytes (divided into eight areas).
total of 384 Mbytes (divided into six areas).
or asynchronous), SDRAM, PCMCIA for each address space.
same space/different space), read-read (in same space/different space), or the first cycle is a
write access.
Features
Section 9
Bus State Controller (BSC)
Rev. 3.00 Jan. 18, 2008 Page 279 of 1458
Section 9
Bus State Controller (BSC)
REJ09B0033-0300

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