HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 241

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

4.3.2
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The
index number can be generated in two different ways depending on the setting of the IX bit in
MMUCR.
1. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
2. When IX = 0, VPN bits 16 to 12 alone are used as the index number
The first method is used to prevent lowered TLB efficiency that results when multiple processes
run simultaneously in the same virtual address space (multiple virtual memory) and a specific
entry is selected by indexing of each process. In single virtual memory mode (MMUCR.SV = 1),
IX bit should be set to 0. Figures 4.8 and 4.9 show the indexing schemes.
number
31
0
Virtual address
31
TLB Indexing
VPN(31 to 17)
Index
VPN(11 to 10)
17
Address Array
16
Figure 4.8 TLB Indexing (IX = 1)
12
11
ASID(7 to 0)
0
Exclusive-OR
V
Way 0 to 3
PPN(28 to 10) PR(1 to 0) SZ
Section 4 Memory Management Unit (MMU)
PTEH register
31
Rev. 3.00 Jan. 18, 2008 Page 179 of 1458
VPN
Data Array
ASID(4 to 0)
10
C
REJ09B0033-0300
0
D
7
SH
ASID
0