HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 916

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
USB Function Controller (USBF)
Figure 25.16 shows the normal operation of the USB function and firmware in isochronous-in
transfer.
EP5 has two up to 64-byte FIFOs, but the user can perform data transmission and write transmit
data without being aware of this dual-FIFO configuration.
In isochronous transfer, transfer occurs only once per one frame (1 ms). So, when SOF is received,
the FIFO buffer is switched automatically with hardware.
FIFO buffers are switched over by the SOF reception. Therefore, the FIFO buffer in which the
USB function transmits the data and the FIFO buffer in which the firmware writes the transmit
data have different buffers, and a read and write of FIFO buffer are not competed. Accordingly,
the data written by the firmware is the data transmitted in one frame after. The buffers of FIFOs
are switched over automatically by the SOF reception, so writing of data must be completed
within the frame.
The USB function transmits data to the host, and the internal TR flag is set to 1, when data to be
transmitted to the host exists in FIFO after an in-token is received. If there is no data in the FIFO
buffer, set the internal TR flag to 1 and transmit 0-byte data to the host.
In firmware, first, the processing routine of the isochronous transfer is called by SOF interrupt to
check the time stamp. Then one packet data is written to FIFO. This written data is transmitted to
the host in the next frame.
SOF happens to be broken because of external cause during transmission from the host. In this
case, an operation flow is different from that in figure 25.16. As an example, figure 25.17 shows
the operation flow of a broken frame and a subsequent frame when SOF is broken once. When
SOF is broken, the FIFO buffer is not switched in corresponding frame, and a time out interrupt
occurs after time set by user has been elapsed.
The firmware detects the SOF break by the time out interrupt. In this case, the FIFO buffer
connected to the CPU has the data to be transmitted in the current frame. If this data is transmitted
in the next frame, the data which is not current one is transmitted. Therefore, the firmware writes
the EP5 CPU clear (FCLR1/EP5 CCLR) to 1. When the SOF interrupt occurs in the subsequent
frame, the processing routine of the isochronous transfer is called and the time stamps are
compared. The time stamps do not much since the SOF break occurred in the previous frame. One
packet of data is written by the firmware according to the transmitted time stamp.
In the frame in which the SOF is broken, the FIFO buffer is not switched and there in no data to be
transmitted to the host. Therefore, USB function controller transmits 0-byte data to the host. Since
the data to be transmitted is cleared by firmware, 0-byte data is transmitted to the host.
Rev. 3.00 Jan. 18, 2008 Page 854 of 1458
REJ09B0033-0300