HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 258

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Memory Management Unit (MMU)
4.6.3
(1)
Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. R0 specifies the write
data and R1 specifies the address.
(2)
This example reads the data section of a specific TLB entry. The bit order indicated in the data
field in figure 4.17 (2) is read. R0 specifies the address and the data section of a selected entry is
read to R1.
4.7
The following operations should be performed in the P1 or P2 area. In addition, when the P0, P3,
or U0 area is accessed consecutively (this access includes instruction fetching), the instruction
code should be placed at least two instructions after the instruction that executes the following
operations.
1. Modification of SR.MD or SR.BL
2. Execution of the LDTLB instruction
3. Write to the memory-mapped TLB
4. Modification of MMUCR
5. Modification of PTEH.ASID
Rev. 3.00 Jan. 18, 2008 Page 196 of 1458
REJ09B0033-0300
; R0=H'1547 381C
; MMUCR.IX=0
; the V bit of way 0 of the entry selected by the VPN(16–12)=B'1 0011
; index is cleared to 0,achieving invalidation.
MOV.L
; R0=H'F300 4300
; MOV.L @R0,R1
Invalidating Specific Entries
Reading the Data of a Specific Entry
Usage Examples
Usage Note
R0,@R1
R1=H'F201 3000
VPN(16-12)=B'00100
Way 3