HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1196

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 33 User Break Controller (UBC)
(Example 1-3)
• Register specifications
(Example 1-4)
• Register specifications
Rev. 3.00 Jan. 18, 2008 Page 1134 of 1458
REJ09B0033-0300
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
After an instruction with ASID = H'80 and address H'00037226 is executed, a user break
occurs before an instruction with ASID = H'70 and address H'0003722E is executed.
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,
BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300000
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
The ASID check is not included.
<Channel B>
Address:
Data:
The ASID check is not included.
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,
no user break occurs since instruction fetch is performed for an even address.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequential mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
H'0003722E, Address mask: H'00000000, ASID = H'70
H'00000000, Data mask: H'00000000
H'00027128, Address mask: H'00000000
H'00031415, Address mask: H'00000000
H'00000000, Data mask: H'00000000
included in the condition)
H'00037226, Address mask: H'00000000, ASID = H'80