HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 745

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.3.1
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
Bit
15
14
13
12
Bit Name
TRMD1
TRMD0
SYNCAT
REDG
Mode Register (SIMDR)
Initial
Value
1
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transfer Mode 1, 0
Select transfer mode. For details, see table 21.2.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
SIOFSYNC Pin Valid Timing
Indicates the position of the SIOFSYNC signal to be
output as a synchronization pulse.
0: At the start-bit data of frame
1: At the last-bit data of slot
Receive Data Sampling Edge
0: The SIOFRxD signal is sampled at the falling edge of
1: The SIOFRxD signal is sampled at the rising edge of
Note: This bit is valid only in master mode.
SIOFSCK (The SIOFTxD signal is transmitted at the
rising edge of SIOFSCK.)
SIOFSCK (The SIOFTxD signal is transmitted at the
falling edge of SIOFSCK.)
Rev. 3.00 Jan. 18, 2008 Page 683 of 1458
Section 21
Serial I/O with FIFO (SIOF)
REJ09B0033-0300