HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1294

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 36
36.4.2
Table 36.4 Reset Configuration
Notes: 1. Performs normal mode and ASE mode settings
36.4.3
The timing of data output from the TDO is switched by the command type set in the SDIR. The
timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,
SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.
When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are
set, TDO is output at the TCK rising edge earlier than the JTAG standard by a half cycle.
Rev. 3.00
REJ09B0033-0300
ASEMD0*
H
L
2. In ASE mode, reset hold is enabled by driving the RESETP and TRST pins low for a
3. In ASE mode, reset may not be enabled. When the emulator is not being connected, set
4. When using this LSI in normal mode, it is recommended that the TRST pin is fixed low.
Reset Configuration
TDO Output Timing
Jan. 18, 2008
1
•
•
ASEMD0 to high.
ASEMD0 = H, normal mode
ASEMD0 = L, ASE mode
constant cycle. In this state, the CPU does not start up, even if RESETP is driven high.
When TRST is driven high, H-UDI operation is enabled, but the CPU does not start up.
The reset hold state is canceled by the following:
User Debugging Interface (H-UDI)
Another RESETP assert (power-on reset)
TRST reassert
RESETP
L
H
L
H
Page 1232 of 1458
TRST*
L
H
L
H
L
H
L
H
4
Chip State
Normal reset and H-UDI reset
Normal reset
H-UDI reset only
Normal operation
Reset hold*
Normal reset*
H-UDI reset only
Normal operation
2
3