HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 287

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 7.1
Exception
Type
Reset
(asynchro-
nous)
General
exception
events
(synchro-
nous)
Current
Instruction
Aborted
Re-executed
Re-executed
Completed
Exception Event Vectors
Exception Event
Power-on reset
Manual reset
User break(before
instruction execution)
CPU address error
(instruction access) *
TLB miss
(instruction access) *
TLB invalid (instruction
access)*
TLB protection violation
(instruction access)*
Illegal general instruction
exception
Illegal slot
instruction exception
CPU address error
(data access)*
TLB miss
(data access)*
TLB invalid
(data access)*
TLB protection violation
(data access)*
Initial page write
(data access)*
Unconditional trap
(TRAPA instruction)
User breakpoint (After
instruction execution,
address)
4
*
5
4
4
4
4
4
*
*
*
*
5
5
5
5
4
4
4
*
*
5
5
Priority*
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Exception
Order
1
2
0
1
1-1
1-2
1-3
2
2
3
3-1
3-2
3-3
3-4
4
5
Rev. 3.00 Jan. 18, 2008 Page 225 of 1458
Process
at BL=1
Reset
Reset
Ignored
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Ignored
Section 7 Exception Handling
Vector
Code
H'000
H'020
H'1E0
H'0E0
H'040
H'040
H'0A0
H'180
H'1A0
H'0E0/
H'100
H'040/
H'060
H'040/
H'060
H'0A0/
H'0C0
H'080
H'160
H'1E0
REJ09B0033-0300
Vector
Offset
—
—
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100