HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 661

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.3.7
SCFER is a 16-bit read-only register that indicates the number of receive data errors (framing
error/parity error).
Bit
15,14
13
12
11
10
9
8
7, 6
5
4
3
2
1
0
FIFO Error Count Register (SCFER)
Bit Name

PER5
PER4
PER3
PER2
PER1
PER0

FER5
FER4
FER3
FER2
FER1
FER0
Initial value R/W
All 0
0
0
0
0
0
0
All 0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Section 18
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Parity Error
Indicates the number of data, in which parity errors
are generated, in receive data stored in the receive
FIFO data register (SCFRDR) in asynchronous mode.
Bits 13 to 8 indicate the number of data with parity
errors after the ER bit in SCSSR is set.
If all 64-byte receive data in SCFRDR have parity
errors, bits PER5 to PER0 indicate 0s.
Reserved
These bits are always read as 0. The write value
should always be 0.
Framing Error
Indicates the number of data, in which framing errors
are generated, in receive data stored in the receive
FIFO data register (SCFRDR) in asynchronous mode.
Bits 5 to 0 indicate the number of data with framing
errors after the ER bit in SCSSR is set.
If all 64-byte receive data in SCFRDR have framing
errors, bits FER5 to FER0 indicate 0s.
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 599 of 1458
REJ09B0033-0300