HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 671

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.3.10 FIFO Control Register (SCFCR)
SCFCR is a 16-bit readable/writable register that resets the number of data in the transmit and
receive FIFO registers, sets the number of trigger data, and contains an enable bit for the loop back
test.
Bit
15
14
13 to 11 
10
9
8
Bit Name
TSE
TCRST
RSTRG2
RSTRG1
RSTRG0
Initial Value R/W
0
0
All 0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
Section 18
Description
Transmit Data Stop Enable
Enables or disables transmit data stop function. This
function is enabled only in asynchronous mode.
Since this function is not supported in synchronous
mode, clear this bit to 0 in synchronous mode.
0: Transmit data stop function disabled
1: Transmit data stop function enabled
Transmit Count Reset
Clears the transmit count to 0. This bit is available
while the transmit data stop function is enabled.
0: Transmit count reset disabled*
1: Transmit count reset enabled (cleared to 0)
Note:
Reserved
These bits are always read as 0. The write value
should always be 0.
Trigger of the RTS Output Active 2 to 0
The RTS signal goes to high, when the number of
receive data count stored in the receive FIFO data
register (SCFRDR) is increased more than the
number of setting triggers listed below.
000: 63
001: 1
010: 8
011: 16
100: 32
101: 48
110: 54
111: 60
*
Serial Communication Interface with FIFO (SCIF)
The transmit count is reset (cleared to 0)
by a power-on reset or manual reset.
Rev. 3.00 Jan. 18, 2008 Page 609 of 1458
REJ09B0033-0300