HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 685

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

If all the above checks are passed, the receive data is stored in SCFRDR.
Note: Even when the receive error (framing error/parity error) is generated, receive operation is
4. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
Figure 18.9 shows an example of the operation for reception.
When modem control is enabled, transmission can be stopped and restarted in accordance with the
CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark
state after transmission of one frame. When CTS is set to 0, the next transmit data is output
starting from the start bit.
interrupt request is generated.
If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt
request is generated.
If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception
interrupt request is generated.
If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive data ready
interrupt request is generated.
Note that a common vector is assigned to each interrupt source.
continued.
Serial
RDF
FER
data
1
Start
Figure 18.9
bit
0
(Example with 8-Bit Data, Parity, One Stop Bit)
D 0 D 1
One frame
Data
D 7
Example of SCIF Receive Operation
Receive-FIFO-data-full
Parity
interrupt request
bit
0/1
Section 18
Stop
bit
1
receive-FIFO-data-ful
Data read and RDF
flag read as 1 then
interrupt handler
Start
cleared to 0 by
bit
0
D 0
Serial Communication Interface with FIFO (SCIF)
D 1
Rev. 3.00 Jan. 18, 2008 Page 623 of 1458
Data
D 7 0/1
Receive-error interrupt
Parity
request generated
by receive error
bit
Stop
bit
1
(mark state)
Idle state
1
REJ09B0033-0300