HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 717

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.5
ICSR performs confirmation of interrupt request flags and status.
Bit
7
6
5
Bit Name
TDRE
TEND
RDRF
I
2
C Bus Status Register (ICSR)
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit Data Register Empty
[Setting condition]
•
•
•
•
[Clearing conditions]
•
•
Transmit End
[Setting conditions]
•
[Clearing conditions]
•
•
Receive Data Register Full
[Setting condition]
•
[Clearing conditions]
•
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When a start condition (including re-transfer) has
been issued
When transmit mode is entered from receive mode in
slave mode
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT with an instruction
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT with an instruction
When a receive data is transferred from ICDRS to
ICDRR
When 0 is written in RDRF after reading RDRF = 1
When ICDRR is read with an instruction
Rev. 3.00 Jan. 18, 2008 Page 655 of 1458
Section 20
I
2
C Bus Interface (IIC)
REJ09B0033-0300
2
C bus