HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 300

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Exception Handling
(2)
If one of the following instructions is executed at the address following RptDtct1, a general illegal
instruction exception occurs. For details on an address to be saved in the SPC, refer to SPC Saved
by an Exception in Repeat Control Period in section 7.4.3, Exception in Repeat Control Period.
• Branch instructions
• Repeat control instructions
• Load instructions for SR, RS, and RE
Note: An extension instruction of this LSI and is not disclosed to the user.
(3)
In the repeat control period, an interrupt or some exception will be retained to prevent an
exception acceptance at an instruction where returning from the exception cannot be performed
correctly. For details, refer to repeat loop program examples 1 to 4. In the examples, exceptions
generated at instructions indicated as [B], [C], ([C1], or [C2]), the following processing is
executed.
• Interrupt, DMA address error
Note: An interrupt request or a DMA address error exception request is retained in the interrupt
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REJ09B0033-0300
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+, Rs
An exception request is not accepted and retained at instructions [B] and [C]. If an instruction
indicates as [A] is executed at the next time, an exception request is accepted.* As shown in
examples 1 to 4, any interrupt or DMA address error cannot be accepted in a repeat loop
consisting of four instructions or less.
Illegal Instruction Exception in Repeat Control Period
An Exception Retained in Repeat Control Period
In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction.
controller (INTC) and the direct memory access controller (DMAC) until the CPU can
accept a request.