HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 510

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10
10.5
Pay attentions to the following notes when the DMAC is used.
10.5.1
When burst mode and cycle steal mode are simultaneously set in two or more channels, an
additional DACK may be asserted at the end of burst transfer. This phenomenon will occur when
all of the conditions described below are satisfied.
1. When the DMA transfer is simultaneously performed in two or more channels support both
2. When the channel to be used in burst mode is set to dual address mode, and DACK is output in
3. When the DMAC cannot obtain the bus mastership consecutively even though a transfer
This phenomenon is avoided by taking either of three measures shown below.
• Measure 1
• Measure 2
• Measure 3
10.5.2
(1)
When DACK is divided for output while the DMAC is accessing an external device, sampling of
DREQ may be accepted once more during the access.
(2)
Conditions: In the cases when DACK is divided for output during external access, specifically, the
following cases:
Rev. 3.00 Jan. 18, 2008 Page 448 of 1458
REJ09B0033-0300
burst mode and cycle steal mode
data write cycle
demand of cycle steal has been received after the completion of burst transfer
After confirming the completion of burst transfer (TE bit = 1), perform the DMA transfer of
other cycle steal mode
The channel to be used in burst mode should not be set to output DACK in data write cycle
When the DMA transfer is simultaneously performed in two or more channels, set all of the
channels to burst mode or cycle steal mode
Overview
Conditions and Phenomena
Usage Notes
Notes on DACK Pin Output
Notes on the Cases When DACK is Divided
Direct Memory Access Controller (DMAC)