HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 245

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 4.1
4.4
4.4.1
There are two kinds of MMU hardware management as follows.
1. The MMU decodes the virtual address accessed by a process and performs address translation
2. In address translation, the MMU receives page management information from the TLB, and
D bit
C bit
PR bit
by controlling the TLB in accordance with the MMUCR settings.
determines the MMU exception and whether the cache is to be accessed (using the C bit). For
details of the determination method and the hardware processing, see section 4.5, MMU
Exceptions.
MMU Functions
MMU Hardware Management
0
1
0
1
00
01
10
11
Access States Designated by D, C, and PR Bits
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
Permitted
Permitted
Permitted
Permitted
Privileged Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation
exception
Permitted
TLB protection
violation
exception
Permitted
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation
exception
TLB protection
violation
exception
Permitted
Permitted
Section 4 Memory Management Unit (MMU)
Rev. 3.00 Jan. 18, 2008 Page 183 of 1458
User Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
TLB protection
violation exception
Permitted
REJ09B0033-0300