HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 844

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 24
Rev. 3.00 Jan. 18, 2008 Page 782 of 1458
REJ09B0033-0300
Bit
31
30 to 16 FSMPS14 to
15, 14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
FIT
FSMPS0

FI13
FI12
FI11
FI10
FI9
FI8
FI7
FI6
FI5
FI4
FI3
FI2
FI1
FI0
USB Host Controller (USBH)
Initial
Value
0
All 0
All 0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Frame Interval Toggle
This bit is toggled by HCD whenever it loads a new value
into FrameInterval.
FS Largest Data Packet
This field specifies a value, which is loaded into the
Largest Data Packet Counter at the beginning of each
frame.
The counter value expresses the largest data amount of
the bit that can be transmitted and received in one
transaction by the host controller at any given time without
causing scheduling overrun. The field value is calculated
by HCD.
Reserved
These bits are always read as 0. The write value should
always be 0.
Frame Interval
These bits specify the interval between two serial SOFs
with bit times. The nominal value is set to 11999. HCD
must store the current value of this field before resetting
the host controller. With this procedure, this bit is reset to
its nominal value by the host controller by setting the HCR
bit in USBHCS. HCD can select to restore the stored value
at the completion of the reset sequence.