HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 260

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Cache
Figure 5.1 shows the cache structure.
(1)
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid. The U bit indicates whether the entry has been written to in write-back mode. When
the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical
address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used
for comparison during cache searches.
In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 9, Bus
State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
(2)
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The
data array is not initialized by a power-on or manual reset.
Rev. 3.00 Jan. 18, 2008 Page 198 of 1458
REJ09B0033-0300
Address Array
Data Array
Entry 255
Entry 0
Entry 1
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24 (1 + 1 + 22) bits
V U Tag address
Address array (ways 0 to 3)
Figure 5.1 Cache Structure
255
0
1
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LW0 to LW3: Longword data 0 to 3
LW0
128 (32 × 4) bits
LW1
LW2
Data array (ways 0 to 3)
LW3
255
0
1
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LRU
6 bits