HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 373

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(2)
• CS0WCR
Bit
5 to 2
1
0
Bit
31 to 21 
20
19, 18
Burst ROM (Clock Asynchronous)
Bit Name
BEN

Bit Name

HW1
HW0
Initial
Value
All 0
0
All 0
Initial
Value
All 0
0
0
R/W Description
R
R/W Burst Enable Specification
R
R/W
R
R/W
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
Enables or disables 8-burst access for a 16-bit bus width or
16-burst access for an 8-bit bus width during 16-byte access.
If this bit is set to 1, 2-burst access is performed four times
when the bus width is 16 bits and 4-burst access is
performed four times when the bus width is 8 bits.
To use a device that does not support 8-burst access or 16-
burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-burst
1: Disables 8-burst access for a 16-bit bus width and 16-burst
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
access for an 8-bit bus width.
access for an 8-bit bus width.
Rev. 3.00 Jan. 18, 2008 Page 311 of 1458
Section 9
Bus State Controller (BSC)
REJ09B0033-0300