HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1117

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

31.3.18 FIFO Pointer Clear Register (FIFOCLR)
The FIFO write/read pointer is cleared by writing any value to FIFOCLR.
31.3.19 DMA Control Register (DMACR)
DMACR sets DMA request signal output. DMAEN enables/disables a DMA request signal. The
DMA request signal is output by a value that has been set to bits SET2 to SET0.
Set this register before executing a multiblock transfer command (CMD18 or CMD25). Auto
mode cannot be used for open-ended multiblock transfer.
Bit
7 to 0
Bit
7
6
5 to 3
Bit Name
FIFOCLR
Bit Name
DMAEN
AUTO
Initial
Value
Initial
Value
0
0
All 0
R/W
W
R/W
R/W
R/W
Description
0: Disables output of DMA request signal. (Initial value)
1: Enables output of DMA request signal.
This bit is set when the pre-defined multiblock transfer
using DMA transfer is performed in auto mode.
0: Auto mode is not used.
1: Auto mode is used.
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
The FIFO pointer is cleared by writing any value to this
register.
Section 31
Rev. 3.00 Jan. 18, 2008 Page 1055 of 1458
MultiMediaCard Interface (MMCIF)
REJ09B0033-0300