HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 364

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9
Rev. 3.00 Jan. 18, 2008 Page 302 of 1458
REJ09B0033-0300
Bit
10
9
8
7
6
5 to 0
Bus State Controller (BSC)
Bit Name
WR3
WR2
WR1
WR0
WM
Initial
Value
1
0
1
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Number of Access Wait Cycles
Specify the number of wait cycles that are necessary for
read or write access.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.

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