HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 730

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 20
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
Rev. 3.00 Jan. 18, 2008 Page 668 of 1458
REJ09B0033-0300
(Master output)
(Master output)
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
(Slave output)
(Slave output)
processing
ICDRR
ICDRS
RDRF
SCL
User
SDA
SCL
SDA
I
2
C Bus Interface (IIC)
Figure 20.11
[2] Read ICDRR (dummy read)
A
9
Bit 7
1
Data 1
Slave Receive Mode Operation Timing (1)
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
8
[2] Read ICDRR
A
9
Bit 7
Data 1
1
Data 2

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