HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 711

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.1
ICCR1 enables or disables the I
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit
7
6
5
4
3 to 0
Bit Name
ICE
RCVD
MST
TRS

I
2
C Bus Control Register 1 (ICCR1)
Initial
Value
0
0
0
0
All 0
2
C bus interface, controls transmission or reception, and selects
R/W
R/W
R/W
R/W
R/W
R
Description
I
0: This module is halted.
1: This bit is enabled for transfer operations.
Reception Disable
This bit enables or disables the next operation when TRS
is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
In master mode with the I
is lost, MST and TRS are both reset by hardware,
causing a transition to slave receive mode. Modification
of the TRS bit should be made between transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data agree
with the slave address that is set to SAR and the eighth
bit is 1, TRS is automatically set to 1.
Operating modes are described below according to MST
and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Reserved
These bits are always read as 0. The write value should
always be 0.
2
C Bus Interface Enable
Rev. 3.00 Jan. 18, 2008 Page 649 of 1458
2
C bus format, when arbitration
Section 20
I
2
C Bus Interface (IIC)
REJ09B0033-0300