HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 353

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.1
CMNCR is a 32-bit register that controls the common items for each area. Do not access external
memory other than area 0 until the CMNCR initialization is complete.
Bit
31 to 15 
14
13
12
11
Common Control Register (CMNCR)
Bit Name
BSD

MAP
BLOCK
0
Initial
Value
All 0
0
0
0
R/W Description
R
R
R/W Space Specification
R/W Bus Access Start Timing Specification After Bus
R/W Bus Lock Bit
Reserved
These bits are always read as 0. The write value should
always be 0.
Acknowledge
Specifies the bus access start timing after the external bus
acknowledge signal is received.
0: Starts the external access at the same timing as the
1: Starts the external access one cycle following the address
Reserved
This bit is always read as 0. The write value should always be
0.
Selects the address map for the external address space. The
address maps to be selected are shown in tables 9.2 and 9.3.
0: Selects address map 1
1: Selects address map 2
Specifies whether or not the BREQ signal is received.
0: Receives BREQ
1: Does not receive BREQ
address drive start after the bus acknowledge signal is
received.
drive start after the bus acknowledge signal is received.
Rev. 3.00 Jan. 18, 2008 Page 291 of 1458
Section 9
Bus State Controller (BSC)
REJ09B0033-0300