HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 354

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9
Rev. 3.00 Jan. 18, 2008 Page 292 of 1458
REJ09B0033-0300
Bit
10
9
8
7
6
5
Bit Name
DPRTY1
DPRTY0
DMAIW2
DMAIW1
DMAIW0
DMAIWA 0
Bus State Controller (BSC)
Initial
Value
0
0
0
0
0
R/W Description
R/W
R/W
R/W
R/W
R/W
R/W Method of Inserting Wait States between Access Cycles when
DMA Burst Transfer Priority
Specify the priority for a refresh request/bus mastership request
during DMA burst transfer.
00: Accepts a refresh request and bus mastership request
01: Accepts a refresh request but does not accept a bus
10: Accepts neither a refresh request nor a bus mastership
11: Reserved (Setting prohibited)
Wait States between Access Cycles when DMA Single Address
is Transferred
Specify the number of idle cycles to be inserted after an access
to an external device with DACK when DMA single address
transfer is performed. The method of inserting idle cycles
depends on the contents of DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycled inserted
100: 6 idle cycled inserted
101: 8 idle cycle inserted
110: 10 idle cycles inserted
111: 12 idle cycled inserted
DMA Single Address is Transferred
Specifies the method of inserting the idle cycles specified by the
DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI
insert the idle cycles when another device, which includes this
LSI, drives the data bus after an external device with DACK
drove it. Setting this bit will make this LSI insert the idle cycles
even when the continuous accesses to an external device with
DACK are performed.
0: Inserts the idle cycles when another device drives the data
1: Inserts the idle cycles every time when an external device
bus after an external device with DACK drove it.
with DACK is accessed.
during DMA burst transfer
mastership request during DMA burst transfer
request during DMA burst transfer