HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 495

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 10.4 shows how the priority changes when channel 0 and channel 3 transfers are requested
simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC
operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 becomes lowest priority.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 becomes lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel
transfer).
waiting)
(channel 3 waits for transfer).
3 becomes the lowest priority.
Figure 10.4
Transfer request
(1) Channels 0 and 3
(3) Channel 1
Waiting channel(s) DMAC operation
Changes in Channel Priority in Round-Robin Mode
1,3
3
3
None
(2) Channel 0 transfer
(4) Channel 0 transfer
(5) Channel 1 transfer
(6) Channel 1 transfer
(7) Channel 3 transfer
(8) Channel 3 transfer
starts
ends
starts
ends
starts
ends
Section 10
Priority order
changes
Priority order
changes
Priority order
changes
Rev. 3.00 Jan. 18, 2008 Page 433 of 1458
Direct Memory Access Controller (DMAC)
Channel priority
0 > 1 > 2 > 3 > 4 > 5
1 > 2 > 3 > 4 > 5 > 0
2 > 3 > 4 > 5 > 0 > 1
4 > 5 > 0 > 1 > 2 > 3
REJ09B0033-0300