HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1476

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 3.00 Jan. 18, 2008 Page 1414 of 1458
REJ09B0033-0300
Item
21.3.9 FIFO Control Register
(SIFCTR)
21.4.7 Transmit and Receive
Procedures
(1) Transmission in Master Mode
Page Revision (See Manual for Details)
701,
702
721
Changed
Figure 21.9 replaced.
Bit
15
14
13
7
6
5
Bit Name Description
TFWM2
TFWM1
TFWM0
RFWM2
RFWM1
RFWM0
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the
10
11
12
8
9
TXE bit should be set to 1.
Clear the TXE bit in SICTR to 0
Set the MSSEL bit in SISCR to 1
Reset the master clock source
Set the FSE bit in SICTR to 0
and BPRS=00000 in SISCR
Start the setting FSE=0,
…
•
•
…
•
•
and baud rate in SISCR
to the TXRST in SISCR
Add pulse (0→1→0)
TXE=0 and other bit.
transmit mode?
Set BRDV=111
Change other
Yes
A transfer request to the transmit
FIFO is issued by the TDREQ bit
in SISTR.
The transmit FIFO is always used
as 16 stages of the FIFO
regardless of these bit settings.
A transfer request to the receive
FIFO is issued by the RDREQ bit
in SISTR.
The receive FIFO is always used
as 16 stages of the FIFO
regardless of these bit settings.
No
End
Set to dis
Synchronize this LSI internal
frame with FSE=0 if restarting
transmit later.
Execute internal initialization
of the bit rate generator
if restarting transmit later.
'No' requires further setting
if transmission is not restarted
(No).
When returning to the same
transmit mode from here,
go back to No.4, FSE setting,
on this flowchart.
Go to "Start" on each flowchart.