MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 130
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chip Configuration Module (CCM)
Advance Information
130
RPLLSEL — PLL Mode Select Bit
RPLLREF — PLL Reference Bit
RLOAD — Pad Driver Load Bit
BOOTPS — Boot Port Size Bit
When the PLL is enabled, the read-only RPLLSEL bit reflects the
default PLL mode.
The default PLL mode can be overridden during reset configuration.
If the default mode is overridden, the PLLSEL bit in the clock module
SYNSR reflects the PLL mode.
When the PLL is enabled in normal PLL mode, the read-only
RPLLREF bit reflects the default PLL reference.
The default PLL reference can be overridden during reset
configuration. If the default mode is overridden, the PLLREF bit in the
clock module SYNSR reflects the PLL reference.
The read-only RLOAD bit reflects the pad driver strength
configuration.
The default function of the pad driver strength can be overridden
during reset configuration. If the default mode is overridden, the
LOAD bit in CCR reflects the pad driver strength configuration.
If the boot device is configured to be external, the read-only BOOTPS
bit reflects the default selection for the boot port size.
The default function of the boot port size can be overridden during
reset configuration. If the default mode is overridden, the PS bit in
CSCR0 reflects the boot device port size configuration.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Normal PLL mode
0 = 1:1 PLL mode
1 = Crystal oscillator is PLL reference.
0 = External clock is PLL reference.
1 = Full drive strength
0 = Default drive strength
1 = Boot device uses 32-bit port.
0 = Boot device uses 16-bit port.
Chip Configuration Module (CCM)
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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