MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 289
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
EPPA[7:0] — EPORT Pin Assignment Select Fields
The read/write EPPAx fields configure EPORT pins for level detection
and rising and/or falling edge detection as
Pins configured as level-sensitive are inverted so that a logic 0 on the
external pin represents a valid interrupt request. Level-sensitive
interrupt inputs are not latched. To guarantee that a level-sensitive
interrupt request is acknowledged, the interrupt source must keep the
signal asserted until acknowledged by software. Level sensitivity
must be selected to bring the device out of stop mode with an INTx
interrupt.
Pins configured as edge-triggered are latched and need not remain
asserted for interrupt generation. A pin configured for edge detection
is monitored regardless of its configuration as input or output.
Interrupt requests generated in the EPORT module can be masked
by the interrupt controller module. EPPAR functionality is
independent of the selected pin direction.
Reset clears the EPPAx fields.
Freescale Semiconductor, Inc.
For More Information On This Product,
EPPAx
00
01
10
11
Edge Port Module (EPORT)
Go to: www.freescale.com
Pin INTx level-sensitive
Pin INTx rising edge triggered
Pin INTx falling edge triggered
Pin INTx both falling edge and rising edge triggered
Table 13-2. EPPAx Field Settings
Pin Configuration
Table 13-2
Edge Port Module (EPORT)
Memory Map and Registers
Advance Information
shows.
289
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