MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 570

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.5.5 HIGHZ Instruction
22.5.6 CLAMP Instruction
22.5.7 BYPASS Instruction
Advance Information
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state until TRST is asserted. While the OnCE TAP controller is enabled,
the top-level JTAG remains transparent.
The HIGHZ instruction is provided as a manufacturer’s optional public
instruction to prevent having to backdrive the output pins during
circuit-board testing. When HIGHZ is invoked, all output drivers,
including the 2-state drivers, are turned off (for example, high
impedance). The instruction selects the Bypass Register. HIGHZ also
asserts internal reset for the system logic to force a predictable internal
state.
The CLAMP instruction selects the Bypass Register and asserts internal
reset while simultaneously forcing all output pins and bidirectional pins
configured as outputs to the fixed values that are preloaded and held in
the Boundary Scan Update Register. This instruction enhances test
efficiency by reducing the overall shift path to a single bit (the Bypass
Register) while conducting an EXTEST type of instruction through the
Boundary Scan Register.
The BYPASS instruction selects the single-bit Bypass Register, creating
a single-bit shift register path from the TDI pin to the Bypass Register to
the TDO pin. This instruction enhances test efficiency by reducing the
overall shift path when a device other than the processor becomes the
device under test on a board design with multiple chips on the overall
IEEE 1149.1 standard defined boundary scan chain. The Bypass
Register has been implemented in accordance with IEEE 1149.1
standard so that the shift register state is set to logic 0 on the rising edge
of TCLK following entry into the capture-DR state. Therefore, the first bit
to be shifted out after selecting the Bypass Register is always a logic 0
(to differentiate a part that supports an IDCODE register from a part that
supports only the Bypass Register).
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA