MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 436

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
19.7 Memory Map
Advance Information
436
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Access results in the module generating an access termination transfer error if not in test mode.
3. Read/writes have no effect and the access terminates with a transfer error exception.
0x00ca_0014–
0x00ca_0200–
0x00ca_0280–
0x00ca_0300–
0x00ca_0380–
0x00ca_0000
0x00ca_0002
0x00ca_0004
0x00ca_0006
0x00ca_0008
0x00ca_000a
0x00ca_000c
0x00ca_000e
0x00ca_0010
0x00ca_0012
0x00ca_027e
0x00ca_037e
only addresses have no effect and result in a cycle termination transfer error.
0x00ca_01fe
0x00ca_02fe
0x00ca_03fe
Address
Port QA Data Register (PORTQA)
Port QA Data Direction Register
The QADC occupies 1 Kbyte, or 512 half-word (16-bit) entries, of
address space. Ten half-word registers are control, port, and status
registers, 64 half-word entries are the CCW table, and 64 half-word
entries are the result table which occupies 192 half-word address
locations because the result data is readable in three data alignment
formats.
Freescale Semiconductor, Inc.
QADC Module Configuration Register (QADCMCR)
Right Justified, Unsigned Result Register (RJURR)
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Left Justified, Unsigned Result Register (LJURR)
(DDRQA)
Left Justified, Signed Result Register (LJSRR)
Table 19-2. QADC Memory Map
MSB
Conversion Command Word Table (CCW)
Table 19-2
QADC Test Register (QADCTEST)
QADC Control Register 0 (QACR0)
QADC Control Register 1 (QACR1)
QADC Control Register 2 (QACR2)
QADC Status Register 0 (QASR0)
QADC Status Register 1 (QASR1)
Go to: www.freescale.com
is the QADC memory map.
Reserved
Reserved
Port QB Data Register (PORTQB)
Port QB Data Direction Register
(3)
(3)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
(DDRQB)
(2)
LSB
Access
MOTOROLA
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
—
S
S
(1)